1. Field of the Invention
The present invention relates to an ESD protection unit, and particularly to an ESD protection unit capable of enhancing trigger-on speed of a low voltage Triggered PNP (LVTPNP) thereby achieving a better ESD performance.
2. Description of the Prior Art
As known, an ESD (Electrostatic Discharge) total-protection design is usually considered as one of the reliability for an integrated circuit (IC). Even through less ESD may cause serious damages on the integrated circuit. For example, during delivery process, such IC products are readily to suffer accidental attacks of various external static electricity, i.e. a HBM (Human Body Model) or MM (Machine Model) ESD stress. Generally speaking, each of the input and output pins of IC products has to sustain HBM ESD stress over ±2000V and MM ESD stress over ±200V. Therefore, ESD protection circuits need be disposed around the input and output (I/O) pads of the IC. Presently, a semiconductor circuit such as a CMOS with an on-chip ESD protection utilizing large amount of diodes or MOS transistors that occupy larger silicon areas. Furthermore, to overcome the high diode reverse-biased breakdown voltage and high MOS transistors holding voltage would cause the ESD protection inefficient.
FIGS. 1–3 are schematic circuit diagrams introducing three traditional ESD protection circuits.
In FIG. 1, the ESD protection device 1 includes two diodes 61, 62 connected between an input pad 103 and a high power supply VDD, and the input pad 103 and a low power supply VSS, respectively. The diode 61 is turned on by a positive ESD pulse across the input pad 103 that flows therefrom to the power supply VDD rather than to the internal circuit 104. Similarly, the diode 62 is turned on by a negative ESD pulse across the input pad 103 that flows therefrom to the power supply VSS rather than to the internal circuit 104.
In FIG. 2, the ESD protection device 2 includes a P-type MOS FET (Metal-oxide semiconductor Field-effect Transistor) 63 and N-type MOS FET 64. Operations of the ESD protection devices 1 and 2 are similar. The transistors 63 and 64 are turned on by a positive and negative ESD pulse across the input pad 103 that flows therefrom to the power supply VDD and VSS, respectively. This protects the internal circuit 104 from being damaged by ESD stress.
Generally speaking, the highest and lowest voltage levels of the input signals of integrated circuits are between the power supply voltages VDD and VSS. However, with the advance of the CMOS manufacturing process, ICs derived from different processes operate at different voltages. For example, the ICs derived from a 0.5 μm CMOS process operate at VDD of 5V, while those derived from a 0.18 μm CMOS process operate at VDD of 1.8V. On a single circuit board, there may be several ICs providing different functions and having I/O pads electrically connected with each other. Thus, each IC may receive I/O signals with different high and low voltage levels. For example, an IC using VDD of 1.8 or 3.3V may receive signals having a high voltage level of 5V output from another IC. This results in an input signal level higher than VDD. Similarly, some situations may cause an input signal lower than VSS. Moreover, in some ICs for network communication, such as ICs receiving signals from a remote device through connection lines, there may be input signals with voltage levels higher than VDD and lower than VSS. The previously described traditional ESD protection devices do not apply to an IC receiving input signals with voltage levels higher than VDD or lower than VSS since they induce leakage currents.
In FIG. 3, the ESD protection device is applicable to ICs receiving input signals with voltage levels lower than VSS. It includes a PNP bipolar junction transistor 67, a silicon controlled rectifier 66 and a PMOS transistor 65. Although this circuit provides ESD protection for ICs receiving input signals with voltage levels lower than VSS, the N well 661 is floated to prevent forward bias of the parasitic diode formed by the junction between the P substrate 662 and N well 661, which makes the silicon controlled rectifier 66 easy to be unintentionally triggered on. This results in latch-up issue to the circuit.
A low voltage triggered PNP (LVTPNP) technology disclosed in a pending U.S. patent application Ser. No. 10/383,643 which now is a publication No. 2004/0085691, just provides an internal circuit with an ESD protection from input signals with voltage level either higher than VDD or lower than Vss, by way of a floating region such as “N+” without usage of any other external trigger signal applied thereon. The disclosure of which is incorporated here. However, since the threshold voltage of the LVTPNP has a higher potential, therefore results in slowing down the conduction speed of the LVTPNP. The internal circuit is still easy to be directly damaged by the ESD stress if ESD current is not able to pass through the LVTPNP in time to the ground. Furthermore, the on-stage high voltage of the LVTPNP device facilitate heat energy rise and may burn itself out at last to result in lost in ESD protection.
Conventional ESD protection circuitry is located between the input pads and the ground potential, VSS and the high voltage, VDD. However, there continues to be a need to prevent damage to the internal circuitry from the increased power supply voltage associated with electrostatic discharge. Thus, it is necessary to design a power clamp circuit disposed between VDD and VSS.
As known, a variety of power clamp circuits have been widely used in ICs. These clamp circuits consist of a primary device to carry the current and a control circuit to condition the primary conduction device to conduct during an ESD event, but not conduct under normal IC operation. The primary conduction devices that have previously been used in CMOS ICs are the NMOS transistor, the PMOS transistor, and a special device called as silicon-controlled rectifier (SCR). Puar in U.S. Pat. No. 5,287,241 describes an ESD network using a PMOS clamp circuit. Ker in U.S. Pat. No. 6,011,681 used an SCR clamp. Each of these primary conduction devices has their respective advantages and disadvantages. The NMOS transistor has a high conductivity, but is itself susceptible to damage by the ESD event. The PMOS transistor is more rugged than the NMOS type, but the PMOS is less than half the conductivity per unit area when compared to the NMOS type. The SCR is both highly conductive and rugged, but difficult to appropriately control. Maloney in U.S. Pat. No. 5,530,612 discusses diodes that function as clamp circuits that result in parasitic PNP transistors for use between isolated power buses.
The clamp circuit requires that the control circuitry be relatively simple, spatially compact, electrically rugged, and also reliable, triggering the conduction of the primary conduction device only during the ESD event. The primary feature of most ESD control circuits is their use of the fast transient nature of the ESD event to trigger the conduction device. The control circuits switch the conducting device to the conducting state when the power bus to ground bus potential increases faster than a certain rate and the increase is greater than a certain value. In some cases, the clamp circuit may become conductive simply when a certain power bus to ground bus potential is exceeded. Dugan in U.S. Pat. No. 5,311,391 describes improvements to the control circuitry and thereby reaching minimum of triggering the ESD conducting device when the IC is in normal operation, but results in consuming additional area and circuit complexity.